Here is a series of address references given as word addresses: 1, 4, 8, 5, 20, 17, 19, 56, 9, 11, 4, 43, 5, 6, 9, 17. Assuming a direct-mapped cache with 16 one-word blocks that is initially empty, label each reference in the list as a hit or a miss and show the final contents of the cache.
Using the series of references given in Exercise 1, show the hits and misses and final cache contents for a direct-mapped cache with four-word blocks and a total size of 16 words.
Compute the total number of bits required to implement the cache in the following Figure 11.1. This number is different from the size of the cache, which usually refers to the number of bytes of data stored in the cache. The number of bits needed to implement the cache represents the total amount of memory needed for storing all of the data, tags, and valid bits.
Using the series of references given in Exercise 1, show the hits and misses and final cache contents for a two-way set-associative cache with one-word blocks and a total size of 16 words. Assume LRU replacement.
Using the series of references given in Exercise 1, show the hits and misses and final cache contents for a two-way set-associative cache with two-word blocks and a total size of 16 words. Assume LRU replacement.
Using the series of references given in Exercise 1, show the hits and misses and final cache contents for a fully associative cache with one-word blocks and a total size of 16 words. Assume LRU replacement.
